verilog

Create fast Fourier transform (FFT) processing hardware for your FPGA or CPLD. Use this tool to create an FFT core of any width or length. Customize to your project's needs. FFT hardware is generated in the SystemVeilog (SV) hardware description language (HDL).

SystemVerilog parser written in C/C++ using flex and bison The scope of this project is parsing SystemVerilog and outputting a serialized version of the abstract syntax tree.